/*
 * Copyright (c) 2025 Paul Wedeck
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_

#define CH32V003_ADC1_DMA 0

#define CH32V003_SPI1_RX_DMA 1
#define CH32V003_SPI1_TX_DMA 2

#define CH32V003_USART1_RX_DMA 4
#define CH32V003_USART1_TX_DMA 3

#define CH32V003_I2C1_RX_DMA 6
#define CH32V003_I2C1_TX_DMA 5

#define CH32V003_TIM1_CH1_DMA 1
#define CH32V003_TIM1_CH2_DMA 2
#define CH32V003_TIM1_CH3_DMA 5
#define CH32V003_TIM1_CH4_DMA 3
#define CH32V003_TIM1_TRIG 3
#define CH32V003_TIM1_COM 3
#define CH32V003_TIM1_UP 4

#define CH32V003_TIM2_CH1_DMA 4
#define CH32V003_TIM2_CH2_DMA 6
#define CH32V003_TIM2_CH3_DMA 0
#define CH32V003_TIM2_CH4_DMA 6
#define CH32V003_TIM2_UP 1

#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_*/
